-bit Serial Binary Addition with Linear Threshold Networks Sorin Cotofana and Stamatis Vassiliadis

In this paper we investigate-bit serial addition in the context of feed-forward linear threshold gate based networks. We show that two n-bit operands can be added in 2d p n e overall delay with a feed-forward network constructed with d p n e + 1 linear threshold gates and 1 2 (5d p n e 2 + 9d p n e) + 2 latches. The maximum weight value is 2 d p n e and the maximum fan-in is 3d p n e+1. We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that, if the weight values are to be limited by a constant W, two n-bit operands can be added in logW] + n log W] overall delay with a feed-forward network that has the implementation cost logW] + 1, in terms of linear threshold gates, 1 2 (55logW] 2 + 99logW]) + 2 in terms of latches, and a maximum fan-in of 33logW] + 1. We also prove that, if the fan-in values are to be limited by a constant F + 1, two n-bit operands can be added in F 3 + n F 3 ] overall delay with a feed-forward network that has the implementation cost F 3 + 1, in terms of linear threshold gates, 1 2 (5 F 3 2 + 9 F 3) + 2 in terms of latches, and a maximumweight value of 2 F 3 ]. An asymptotic bound of O(n logn) is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e. in the order of O(n). The implementation cost in this case is in the order of O(log n), in terms of linear threshold gates, and in the order of O(log 2 n), in terms of latches. The maximum fan-in is in the order of O(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented.